In this post I will explain a circuit that can come in quite handy if one tries to switch a high voltage but can’t use an integrated circuit. A reason why it’s sometimes not possible to use an integrated solution is, because most ICs only work up to a certain voltage. Furthermore, the presence of voltage spikes can be a real problem in noisy environments.
Goals of the circuit
- high voltages – Circuit that can switch on/off a voltage bus and also have the possibility to switch high voltages
- TTL/CMOS logic – The circuit shall be controlled by a simple TTL or CMOS logic signal.
- high-side switch – The switch mechanism shall be a high-side switch. High side switches have several advantages over low side switching, especially if you connect with non isolated signals to other modules.
- cheap – the solution should be cheap, therefore only readily available components can be used
- easy – the component count should be kept as low as possible
- DC voltage
If we try to switch any voltage we basically have the following options: transistor (FET, bipolar), relay, thyristor. In this post we will use MOSFETs and see how we manage to switch quite a high voltage in the high-side configuration.
I will assume that you know the basics about MOSFET. Therefore, I will only highlight the important difference between N-/P-MOSFETs that are related to the present situation.
N-MOSFETs usually have a lower rdson resistance, which makes them perfect for high current switches used in low-side switches. Furthermore, they can easily be controlled by any CMOS or even TTL logic signal. There are also various MOSFET drivers available that are used in high speed high current switching applications, where the gate charge can significantly slow down the switching time.
The biggest draw back of NMOS is that they can only be controlled directly by logic if the low-side switch configuration is used. That means that the NMOS is interrupting the ground path. Therefore, the voltage difference at the output becoming zero. However, this can lead to certain problems if you are having a bigger system with multiple devices all referenced
to GND and some potential. In the case where you have some logic lines or communication lines connecting the multiple devices, it can be real problem if you use the ground- or low-side switching circuit topology. I will try to quickly explain the situation in the figure below.
The example on the right should explain the reason for the problem pretty well. Please note that the example is set up so that it fails, nobody would implement any device in such a simplistic matter like that. The figure shows two devices (in the rectangular boxes) that are connected by a communication line (open drain output). The second device has a diode D1 for input protection. One device is powered with 50V, the other with 5V. Both are referenced to the same GND. If we close the switch S1, then everything is fine, both devices have a strong GND potential, the motor M1 spins and we can communicate without any issues at all. At this point the communication line has a voltage of about 4.5V (depending on the resistor divider R1, R2). Now lets look at what happens if we open S1 and turn off the first device (motors stops spinning). The first device will lose its ground connection, which will cause any line of the first device to float to 50V. That isn’t a problem for the first device at all, since the voltage difference of its supply terminals to its GND terminals is 0V (because the GND terminal of device 1 is not connected to GND anymore!). However, the second device isn’t happy at all. The device on the left floats to 50V, which also means that the communication line will rise to 50V. As soon as the breakdown voltage of D1 is reached, D1 will essentially short the communication line to GND. The current that flows in that moment only depends on R1. It can be a high enough current to effectively destroy the device on the right side. Remember, the problem only occurred, because one device lacks a GND reference, but the other one is still referenced to GND.
Note: the solution to this problem would be to use the N-MOS in a high-side switch topology, however then it becomes quite hard to actually apply a high enough control voltage in the case of our example. Essentially, the Ugs has to be at least 5-15V higher than the voltage we are trying to switch! It’s not impossible to use nmos as high-side switches, but it’s just much more effort to get it to work. Some keywords on the topic: charge pump, isolated dc/dc converter, high-side driver IC
P-MOSFETs usually have a higher rdson than N-MOS and are not perfectly suited for high power applications. They can easily be used in low- or high-side switching topologies for low voltages. However, if we try to switch a high voltage we have the same problem as with the N-MOS. However, in this case the problem isn’t as bad as before, because Ugs only needs to be between 5-15V LOWER than the voltage we are trying to switch. This condition can be achieved much easier, as we will see in the next chapter.
P-MOS high-side switch
So we try to switch a relatively high voltage with a p-mos in the high-side topology, but we want to control our switching circuit with a simple logic signal TTL or CMOS. Almost all our goals can be achieved with the circuit below. We are using a p-mos as a high-side switch, but control it with an n-mos in low-side configuration. If there is no voltage on P3 -> Up3=0V, then Q1 is non-conductive and the gate of Q2 will float to our input voltage Up1. Therefore, Q2 will stay turned off and there will be no current flow through Q2.
If we apply a voltage of about 5-15V (depending on Q1) on Up3, Q1 becomes conductive and pulls the potential of Q2’s gate lower. The two resistors R1 and R2 have to be dimensioned, so that if Q1 is conductive the voltage difference of Q2’s gate to Up1 is at least minus 5-15V (depending on Q2). Therefore, if we apply a logic signal to Up3, first Q1 becomes conductive pulls down the gate of Q2 and then Q2 becomes conductive too and we have a current flow through Q2. The basic functionality of the circuit is now explained. Before I conclude my post, lets have a look at D1. D1 is a Z-diode with a breakdown voltage of about 5-15V (dimensioned according Q2’s parameters). D2 is protecting Q2 so that the voltage difference of Ugs to Up1 can’t become too high, which might destroy Q2. Therefore, even if our input voltage Up1 is not stable and varies or has high voltage peaks, we can still switch Q2 with quite a good reliability (e.g battery will have quite a high voltage difference between fully charged and depleted).
Limitations of this circuit
Let’s talk a little about the drawbacks of the explained circuit.
- p-mos – because we are using a p-mos as the main switch (where the most current flows), this circuit is not suited for high power applications (higher rdson than nmos)
- high-speed – every mosfet has a certain gate charge. This capacitor has to get charged every time the mosfet switches, therefore in high-speed applications we would like to apply a strong driver circuit in order to quickly charge the gate capacity (otherwise the losses in the mosfet will be very high). The problem with the circuit is that we can’t really charge it that fast, since our charging/decharging current depends on R1 and R2. The only choice we have, is to compromise on wasted current and charging time.
In this post, we had a look at low- and high-side switching with n-mosfet and p-mosfets. Next, we briefly talked about some advantages of n-mos and p-mosfets. Furthermore, we talked about a circuit that uses both n-mos and p-mos in high- and low-side switching topology in order to switch a high voltage with a TTL or CMOS logic signal. Finally, we covered some of the limitations that this circuit has. I hope you enjoyed this post, please leave any comments in the comment section below 🙂